With the development of semiconductor designs and manufacturing techniques, it is desired to decrease power consumption while reducing the size of a semiconductor device to improve the integration level. In order to suppress a short channel effect caused by a shrinkage of size, a FinFET formed on a SOI wafer or a bulk semiconductor substrate has been proposed. The FinFET may comprise a channel region formed between the fins of semiconductor material and source/drain regions formed in both ends of the fin. A gate electrode at least surrounds the channel region at both sides of the channel regions (i.e. a dual-gate structure) so as to form an inversion layer at the respective sides of the channel. Since the whole channel region is controlled by the gate, it plays a role of suppressing the short channel effect. In order to decrease power consumption caused by leakage, an ultra-thin buried oxide body (UTTB) type FET formed in a semiconductor substrate has been proposed. The UTTB-type FET may comprise an ultra-thin buried oxide layer in the semiconductor substrate, a front gate and source/drain region over the ultra-thin buried oxide layer and a back gate below the ultra-thin buried oxide layer. In operation, power consumption may be remarkably reduced while speed is kept constant by applying a bias voltage to the back gate.
Although there are respective advantages for both solutions, a semiconductor device which incorporates advantages of both solutions has not been proposed, since it is difficult to form a back gate in a FinFET. In a FinFET based on a bulk semiconductor substrate, since the contact surface area of the semiconductor Fin and the semiconductor substrate is very small, the formed back gate will lead to a serious spontaneous heating effect. In a FinFET based on an SOI wafer, the expensive price of the SOI wafer leads to a problem of high cost. In addition, it needs precisely controlled ion implantation when a back gate is formed in the SOI wafer so as to form an implantation region for the back gate below the buried insulation layer and penetrating through the top semiconductor layer, which leads to difficulty of process to make a lower rate of finished products. The unintended doping for the channel region leads to fluctuating of device performance.